XConn Unveils Hybrid PCIe Gen 6.2 and CXL 3.1 Solution at FMS25

XConn Unveils Hybrid PCIe Gen 6.2 and CXL 3.1 Solution at FMS25

Key Points

  • XConn will demo an end‑to‑end PCIe Gen 6.2 and CXL 3.1 solution at the FMS25 event.
  • The Apollo 2 switch is the first hybrid chip to support both standards simultaneously.
  • Partnerships with Intel and ScaleFlux aim to ensure smooth hardware‑software integration and broader CXL 3.1 support.
  • The solution targets AI/ML training, cloud computing, composable infrastructure, and high‑speed storage applications.
  • Real‑world performance data and benchmarks are not yet available, keeping actual impact uncertain.

The next stage in AI power? XConn set to reveal end-to-end PCIe Gen 6 offering higher bandwidth than ever

Background

XConn Technologies announced that it will demonstrate a fully integrated, end‑to‑end PCIe Gen 6.2 and CXL 3.1 solution at the upcoming Future of Memory and Storage (FMS25) event. The company frames the demonstration as a critical step toward meeting the performance needs of artificial‑intelligence (AI) and data‑center workloads that demand higher bandwidth and lower latency.

Apollo 2 Hybrid Switch

The centerpiece of the showcase is the Apollo 2 switch, marketed as the industry’s first hybrid switch to support both PCIe Gen 6.2 and CXL 3.1 within a single chip. XConn says the integration simplifies interconnect designs, reduces complexity in data‑center architectures, and enhances scalability for a range of applications, from AI/ML model training to cloud computing and composable infrastructure.

“XConn is excited to bring to market PCIe Gen 6.2 and CXL 3.1 switches, with samples now available,” said Gerry Fan, CEO of XConn Technologies. “As the industry accelerates toward more memory‑centric and performance‑intensive architectures, our commitment is to empower customers with best‑in‑class.”

Collaboration with Intel

XConn highlighted a partnership with Intel, noting that Intel Senior Fellow Ronak Singhal described the collaboration as a way to ensure that software and hardware components interact smoothly, delivering “robust end‑to‑end solutions.” The joint effort is intended to foster an interoperable environment for both PCIe and CXL technologies, helping customers adopt the new standards without extensive redesign.

ScaleFlux Partnership

In addition to Intel, XConn has partnered with ScaleFlux to improve CXL 3.1 interoperability for AI and cloud infrastructure. This alliance aims to broaden the ecosystem support for the emerging CXL standard, although specific performance outcomes have not yet been disclosed.

Demo Expectations and Industry Impact

The upcoming demo will showcase low‑latency, high‑bandwidth switching and is positioned as a preview of how the technology could serve AI/ML training, cloud workloads, and composable infrastructure. XConn also suggests that the solution could have significant implications for high‑speed storage, potentially supporting larger SSD capacities and faster data transfers between storage devices and processing units.

While the theoretical benefits are compelling, the company acknowledges that real‑world scalability, reliability, and benchmark results are still pending. Observers note that successful validation often requires multiple demo cycles and production‑grade testing.

Cautious Outlook

Industry analysts caution that, despite the promising architecture, the actual advantage of integrating PCIe Gen 6.2 and CXL 3.1 on a single chip will depend on performance outcomes under production workloads. Until benchmark data is released, it remains difficult to quantify the improvement over existing PCIe Gen 5 deployments.

Overall, XConn’s announcement signals momentum toward more memory‑centric, high‑bandwidth interconnect solutions, but the technology’s impact will be measured once field data validates the claimed benefits.

Source: techradar.com